library verilog;
use verilog.vl_types.all;
entity top_vlg_sample_tst is
    port(
        clk_1khz        : in     vl_logic;
        \mod\           : in     vl_logic;
        rst             : in     vl_logic;
        \select\        : in     vl_logic;
        set             : in     vl_logic;
        stop            : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end top_vlg_sample_tst;
